A digital integrated circuit design intended for mass-production may be modified to include testing capabilities. For example, integrated circuit designers may incorporate circuit components within an integrated circuit design that facilitate testing of an integrated circuit chip. Such components, embedded within a produced circuit, in conjunction with an automatic test pattern generator, may allow a chip that is produced based on the integrated circuit design to be tested before being packaged within a final product. One testing technique used in the integrated circuit industry is referred to as a scan, or scan testing. The scan testing technique may include loading and unloading data to/from respective memory elements in an integrated circuit through external leads. For example, test data may be loaded, or shifted in, to memory elements, e.g. flip-flops, within an integrated circuit via one or more scan test chains in preparation for conducting a test of combinational logic within the integrated circuit. Once the test input data is shifted in, combinational logic within the integrated circuit may be executed for one or more cycles to generate test output data that is stored within memory elements, e.g. flip-flops, of the one or more scan test chains. The resulting test output data may then be unloaded, or shifted out, via the one or more scan chains. A load/unload process may be referred to as a scan-shift flow. A scan-shift flow with a single capture is called a combinational flow and flow with a repeating capture event may be called a sequential flow. All capture events except for the last capture in a sequential flow may be called launch events and the last capture event may be called a capture.
An integrated circuit design tool may support simulated testing of an integrated circuit design that supports scan testing. Such an integrated circuit design tool may generate a fault coverage, typically a number between 90% and 99%, that refers to the percentage of possible faults that the design tool determines would be detected during the testing of an actual integrated circuit chip. Adapting a circuit to support scan chain testing may significantly increase the complexity of the circuit by requiring, for example, the inclusion of external scan input leads, the inclusion of external scan output leads, the inclusion of a scan enable lead, the inclusion of a scan control element, e.g., a multiplexor, for each flip-flop, and the routing of additional control lead and data lead connections. Such additional components and leads adversely affect, i.e., increase, the area, routing, power consumption and heat dissipation requirements of the circuit. Further, such additional features may increase the minimum clock cycle time, thereby decreasing the maximum frequency that may be achieved by the circuit.
In a full scan design, all memory elements, e.g., flip-flops, used to store input data to, and output data from, combinational logic within an integrated circuit, may be converted to scan-enabled memory elements e.g., multiplexed flip-flops connected in a scan chain that supports scan chain testing. In a partial scan design, only a selected portion of the memory elements may be converted to scan-enabled memory elements. For designs that are sensitive to area and/or performance overhead, a test approach using a sequential flow and a partial scan offers an attractive alternative to the full-scan test approach. By reducing the number of scan-enabled memory elements using a partial scan approach, the adverse impact on circuit performance, addressed above, may be reduced. However, reducing the number of scan-enabled memory elements also reduces the fault coverage that is achieved. Therefore, a significant issue faced by integrated circuit designers is how to reduce the number of scan-enabled memory devices included in an integrated circuit design, without reducing the fault coverage achieved with the subsequent partial scan testing.